FULBRING

Introduction

This section discusses the AVR core architecture in general. The main function of the CPU coreis to ensure correct program execution. The CPU must therefore be able to access memories,perform calculations, control peripherals, and handle interrupts.

Architectural Overview

Figure 2.  Block Diagram of the AVR MCU Architecture.

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – withseparate memories and buses for program and data. Instructions in the Program memory areexecuted with a single level pipelining. While one instruction is being executed, the next instruc-tion is pre-fetched from the Program memory. This concept enables instructions to be executedin every clock cycle. The Program memory is In-System Reprogrammable Flash memory.The fast-access Register File contains 32 x 8-bit general purpose working registers with a singleclock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-ical ALU operation, two operands are output from the Register File, the operation is executed,and the result is stored back in the Register File – in one clock cycle.Six of the 32 registers can be used as three 16-bit indirect address register pointers for DataSpace addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. Theseadded function registers are the 16-bit X-, Y-, and Z-register, described later in this section.The ALU supports arithmetic and logic operations between registers or between a constant anda register. Single register operations can also be executed in the ALU. After an arithmetic opera-tion, the Status Register is updated to reflect information about the result of the operation.The Program flow is provided by conditional and unconditional jump and call instructions, able todirectly address the whole address space. Most AVR instructions have a single 16-bit word for-mat. Every Program memory address contains a 16- or 32-bit instruction.Program Flash memory space is divided in two sections, the Boot program section and theApplication program section. Both sections have dedicated Lock Bits for write and read/writeprotection. The SPM instruction that writes into the Application Flash memory section mustreside in the Boot program section.During interrupts and subroutine calls, the return address Program Counter (PC) is stored on theStack. The Stack is effectively allocated in the general data SRAM, and consequently the Stacksize is only limited by the total SRAM size and the usage of the SRAM. All user programs mustinitialize the SP in the reset routine (before subroutines or interrupts are executed). The StackPointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessedthrough the five different addressing modes supported in the AVR architecture.The memory spaces in the AVR architecture are all linear and regular memory maps.A flexible interrupt module has its control registers in the I/O space with an additional globalinterrupt enable bit in the Status Register. All interrupts have a separate Interrupt Vector in theInterrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-tion. The lower the Interrupt Vector address, the higher the priority.The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the DataSpace locations following those of the Register File, 0x20 - 0x5F.

Arithmetic Logic Unit – ALU

The high-performance AVR ALU operates in direct connection with all the 32 general purposeworking registers. Within a single clock cycle, arithmetic operations between general purposeregisters or between a register and an immediate are executed. The ALU operations are dividedinto three main categories – arithmetic, logical, and bit-functions. Some implementations of thearchitecture also provide a powerful multiplier supporting both signed/unsigned multiplicationand fractional format. See the “Instruction Set” section for a detailed description.

Status Register

The Status Register contains information about the result of the most recently executed arithme-tic instruction. This information can be used for altering program flow in order to performconditional operations. Note that the Status Register is updated after all ALU operations, asspecified in the Instruction Set Reference. This will in many cases remove the need for using thededicated compare instructions, resulting in faster and more compact code.The Status Register is not automatically stored when entering an interrupt routine and restoredwhen returning from an interrupt. This must be handled by software.The AVR Status Register – SREG – is defined as:

•Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-rupt enable control is then performed in separate control registers. If the Global Interrupt EnableRegister is cleared, none of the interrupts are enabled independent of the individual interruptenable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set bythe RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared bythe application with the SEI and CLI instructions, as described in the Instruction Set Reference.

•Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-nation for the operated bit. A bit from a register in the Register File can be copied into T by theBST instruction, and a bit in T can be copied into a bit in a register in the Register File by theBLD instruction.

•Bit 5 – H: Half Carry Flag 

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is usefulin BCD arithmetic. See the “Instruction Set Description” for detailed information.

•Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s ComplementOverflow Flag V. See the “Instruction Set Description” for detailed information.

•Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the“Instruction Set Description” for detailed information.

•Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the“Instruction Set Description” for detailed information.

•Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “InstructionSet Description” for detailed information.

•Bit 0 – C: Carry Flag

The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction SetDescription” for detailed information.

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achievethe required performance and flexibility, the following input/output schemes are supported by theRegister File:

•One 8-bit output operand and one 8-bit result input.

•Two 8-bit output operands and one 8-bit result input.

•Two 8-bit output operands and one 16-bit result input.

•One 16-bit output operand and one 16-bit result input.

Figure 3 shows the structure of the 32 general purpose working registers in the CPU.

Figure 3.  AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, andmost of them are single cycle instructions.As shown in Figure 3, each register is also assigned a Data memory address, mapping themdirectly into the first 32 locations of the user Data Space. Although not being physically imple-mented as SRAM locations, this memory organization provides great flexibility in access of theregisters, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.

The X-register, Y-register and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-isters are 16-bit address pointers for indirect addressing of the Data Space. The three indirectaddress registers X, Y and Z are defined as described in Figure 4.

Figure 4.  The X-, Y- and Z-Registers

In the different addressing modes these address registers have functions as fixed displacement,automatic increment, and automatic decrement (see the Instruction Set Reference for details).

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storingreturn addresses after interrupts and subroutine calls. The Stack Pointer Register always pointsto the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-tions to lower memory locations. This implies that a Stack PUSH command decreases the StackPointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and InterruptStacks are located. This Stack space in the data SRAM must be defined by the program beforeany subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set topoint above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stackwith the PUSH instruction, and it is decremented by two when the return address is pushed ontothe Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data ispopped from the Stack with the POP instruction, and it is incremented by two when address ispopped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number ofbits actually used is implementation dependent. Note that the data space in some implementa-tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVRCPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for thechip. No internal clock division is used.

Figure 5 shows the parallel instruction fetches and instruction executions enabled by the Har-vard architecture and the fast-access Register File concept. This is the basic pipelining conceptto obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,functions per clocks, and functions per power-unit.

Figure 5.  The Parallel Instruction Fetches and Instruction Executions 

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate ResetVector each have a separate Program Vector in the Program memory space. All interrupts areassigned individual enable bits which must be written logic one together with the Global InterruptEnable bit in the Status Register in order to enable the interrupt. Depending on the ProgramCounter value, interrupts may be automatically disabled when Boot Lock Bits BLB02 or BLB12are programmed. This feature improves software security. See the section “Memory Program-ming” on page 222 for details.

The lowest addresses in the Program memory space are by default defined as the Reset andInterrupt Vectors. The complete list of Vectors is shown in “Interrupts” on page 46. The list alsodetermines the priority levels of the different interrupts. The lower the address the higher is thepriority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request0. The Interrupt Vectors can be moved to the start of the boot Flash section by setting the Inter-rupt Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to“Interrupts” on page 46 for more information. The Reset Vector can also be moved to the start ofthe boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 209. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabledinterrupts can then interrupt the current interrupt routine. The I-bit is automatically set when aReturn from Interrupt instruction – RETI – is executed. 

There are basically two types of interrupts. The first type is triggered by an event that sets theInterrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-tor in order to execute the interrupt handling routine, and hardware clears the correspondingInterrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit iscleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag iscleared by software. Similarly, if one or more interrupt conditions occur while the global interruptenable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until theglobal interrupt enable bit is set, and will then be executed by order of priority. 

The second type of interrupts will trigger as long as the interrupt condition is present. Theseinterrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before theinterrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute onemore instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, norrestored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with theCLI instruction. The following example shows how this can be used to avoid interrupts during thetimed EEPROM write sequence.

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-cuted before any pending interrupts, as shown in the following example.

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-mum. After four clock cycles, the Program Vector address for the actual interrupt handlingroutine is executed. During this 4-clock cycle period, the Program Counter is pushed onto theStack. The Vector is normally a jump to the interrupt routine, and this jump takes three clockcycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is com-pleted before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, theinterrupt execution response time is increased by four clock cycles. This increase comes in addi-tion to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clockcycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incre-mented by 2, and the I-bit in SREG is set.

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